EP910ILC-15N vs EP910ILC-25 比較
詳細な並列比較: EP910ILC-15N メーカー: Altera および EP910ILC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
仕様比較
| パラメータ | EP910ILC-15N | EP910ILC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $9.95 |
| Family | Classic | EP910 Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O Pins | 36 | 36 |
| Dedicated Input Pins | 16 | — |
| パッケージ | PLCC-44 (J-lead, surface mount) | 44-pin JLCC (windowed ceramic) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS ステータス | Compliant | non_compliant (ceramic windowed package) |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 25 ns |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| 電源電圧 | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| ライフサイクル状態 | — | Obsolete - last time buy was late 1990s |