EP910ILC-15N vs EP910ILC-25 Comparaison
Comparaison détaillée côte à côte de EP910ILC-15N par Altera et EP910ILC-25 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Comparaison des spécifications
| Paramètre | EP910ILC-15N | EP910ILC-25 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,85 | $9,95 |
| Family | Classic | EP910 Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O Pins | 36 | 36 |
| Dedicated Input Pins | 16 | — |
| Boîtier | PLCC-44 (J-lead, surface mount) | 44-pin JLCC (windowed ceramic) |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Statut RoHS | Compliant | non_compliant (ceramic windowed package) |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 25 ns |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Tension d'alimentation | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Statut du cycle de vie | — | Obsolete - last time buy was late 1990s |