EP910ILC-15N vs EP910ILI-25 比較
詳細な並列比較: EP910ILC-15N メーカー: Altera および EP910ILI-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete仕様比較
| パラメータ | EP910ILC-15N | EP910ILI-25 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $7.25 |
| Family | Classic | — |
| Product Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O Pins | 36 | — |
| Dedicated Input Pins | 16 | — |
| パッケージ | PLCC-44 (J-lead, surface mount) | PLCC-44 (windowed ceramic, J-lead) |
| 実装タイプ | Surface Mount | — |
| 動作温度 | 0 C to +70 C (commercial) | -40C to +85C (Industrial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS ステータス | Compliant | Non-compliant (windowed ceramic package) |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Series | — | EP910 (Classic EPLD) |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 (maximum) |
| Propagation Delay (tPD) | — | 25 ns |
| Technology | — | CMOS, EPROM |
| Architecture | — | PAL-type with global interconnect bus |
| Operating Voltage | — | 5 V (4.75 V to 5.25 V) |
| Programming Method | — | UV-erasable (windowed), MAX+PLUS II programmer |
| Logic Test Circuitry | — | On-board JTAG-compatible test |