EP910ILI-25 vs EP910ILC-12 比較
詳細な並列比較: EP910ILI-25 メーカー: Altera および EP910ILC-12 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910ILI-25 | EP910ILC-12 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.25 | $12.40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | 12 ns (max) |
| Technology | CMOS, EPROM | — |
| Architecture | PAL-type with global interconnect bus | — |
| パッケージ | PLCC-44 (windowed ceramic, J-lead) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| 動作温度 | -40C to +85C (Industrial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | Altera programming algorithm (serial/parallel master-slave) |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| RoHS ステータス | Non-compliant (windowed ceramic package) | [DATA_NEEDED: RoHS status] |
| Family | — | Altera EP910 Classic EPLD |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 (typical) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| 実装タイプ | — | Surface Mount |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| MSLレベル | — | [DATA_NEEDED: MSL level] |
| ピン数 | — | 28 |
| Feedback Paths | — | 16 dedicated |