EP910ILI-25 vs EP910IPC-50 比較
詳細な並列比較: EP910ILI-25 メーカー: Altera および EP910IPC-50 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910ILI-25 | EP910IPC-50 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.25 | $13.85 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | 50 ns |
| Technology | CMOS, EPROM | CMOS EPROM cell |
| Architecture | PAL-type with global interconnect bus | — |
| パッケージ | PLCC-44 (windowed ceramic, J-lead) | 40-pin Ceramic DIP (IPC, windowed) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| 動作温度 | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | Off-board EPROM programmer + UV erase |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| RoHS ステータス | Non-compliant (windowed ceramic package) | [DATA_NEEDED: not stated in verified data] |
| Family | — | Altera Classic EPLD |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Erasure Method | — | UV light through ceramic window (IPC package) |
| 実装タイプ | — | Through-Hole (DIP) |