EP910ILI-25 vs EP910IPC-50 Comparação
Comparação detalhada lado a lado de EP910ILI-25 por Altera e EP910IPC-50 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP910ILI-25 | EP910IPC-50 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $7,25 | $13,85 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | 50 ns |
| Technology | CMOS, EPROM | CMOS EPROM cell |
| Architecture | PAL-type with global interconnect bus | — |
| Encapsulamento | PLCC-44 (windowed ceramic, J-lead) | 40-pin Ceramic DIP (IPC, windowed) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| Temperatura de operação | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | Off-board EPROM programmer + UV erase |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| Status RoHS | Non-compliant (windowed ceramic package) | [DATA_NEEDED: not stated in verified data] |
| Family | — | Altera Classic EPLD |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Erasure Method | — | UV light through ceramic window (IPC package) |
| Tipo de montagem | — | Through-Hole (DIP) |