EP910IPC-25 vs EP910PC-0 比較
詳細な並列比較: EP910IPC-25 メーカー: Intel および EP910PC-0 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910IPC-25 | EP910PC-0 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $8.70 |
| Family | Classic EPLD (EP910 series) | Classic EPLD |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | — |
| Usable Gates | 450 | 900 gates |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | — |
| 動作温度 | 0C to +70C (commercial grade) | 0C to +70C (commercial) |
| パッケージ | 40-pin PDIP (PDIP-40) | PDIP-40 (Plastic DIP, 40-pin) |
| 実装タイプ | Through-Hole | Through-Hole (DIP) |
| Programming Method | EPROM cell (OTP / UV erasable) | UV-erasable / OTP |
| Development Tool | MAX+PLUS II | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Blocks | — | 6 (4 macrocells each) |
| I/O Pins | — | 24 |
| Speed Grade | — | -0 (slowest) |
| 電源電圧 | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |