EP910LC-40 vs EP910LC-40H 比較
詳細な並列比較: EP910LC-40 メーカー: Rochester Electronics および EP910LC-40H メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsolete
仕様比較
| パラメータ | EP910LC-40 | EP910LC-40H |
|---|---|---|
| ブランド | Rochester Electronics | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $52.00 | $9.95 |
| Manufacturer | Rochester Electronics (Altera original) | — |
| Device Family | Altera Classic EPLD - EP910 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 450 | 450 |
| Macrocells | 24 | — |
| Logic Array Blocks | 2 (12 macrocells each) | — |
| Propagation Delay (tPD) | 40 ns | 40 ns max |
| Maximum Toggle Frequency (fMAX) | 25 MHz | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM |
| パッケージ | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) | 40-pin Ceramic DIP (CDIP-40), JEDEC standard |
| Operating Temperature (Commercial) | 0 C to +70 C | — |
| Programming Method | Altera Logic Programmer (PLAD-J), 4-wire serial | UV-erase + EPROM program, ~100 erase cycles |
| RoHS ステータス | Not applicable (legacy) | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] |
| Lead-Free Status | Not applicable | — |
| Family | — | Classic EPLD (EP910) |
| Macro Cells | — | 24 |
| Logic Elements | — | 24 macro cells / expandable to 48 via expander terms |
| Supply Current (ICC) | — | Low-power CMOS, typical ICC < 100 mA |
| 実装タイプ | — | Through-Hole (THT) |
| 動作温度 | — | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] |
| Speed Grade | — | -40 (40 ns tPD) |
| I/O Pins | — | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] |