EP910LC-40 vs EP910LC-40H 비교
다음의 상세 나란히 비교: EP910LC-40 제조: Rochester Electronics 및 EP910LC-40H 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsolete
사양 비교
| 파라미터 | EP910LC-40 | EP910LC-40H |
|---|---|---|
| 브랜드 | Rochester Electronics | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $52.00 | $9.95 |
| Manufacturer | Rochester Electronics (Altera original) | — |
| Device Family | Altera Classic EPLD - EP910 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 450 | 450 |
| Macrocells | 24 | — |
| Logic Array Blocks | 2 (12 macrocells each) | — |
| Propagation Delay (tPD) | 40 ns | 40 ns max |
| Maximum Toggle Frequency (fMAX) | 25 MHz | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM |
| 패키지 | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) | 40-pin Ceramic DIP (CDIP-40), JEDEC standard |
| Operating Temperature (Commercial) | 0 C to +70 C | — |
| Programming Method | Altera Logic Programmer (PLAD-J), 4-wire serial | UV-erase + EPROM program, ~100 erase cycles |
| RoHS 상태 | Not applicable (legacy) | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] |
| Lead-Free Status | Not applicable | — |
| Family | — | Classic EPLD (EP910) |
| Macro Cells | — | 24 |
| Logic Elements | — | 24 macro cells / expandable to 48 via expander terms |
| Supply Current (ICC) | — | Low-power CMOS, typical ICC < 100 mA |
| 실장 유형 | — | Through-Hole (THT) |
| 동작 온도 | — | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] |
| Speed Grade | — | -40 (40 ns tPD) |
| I/O Pins | — | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] |