EP910LC-40 vs EP910LC44 比較
詳細な並列比較: EP910LC-40 メーカー: Rochester Electronics および EP910LC44 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsolete
仕様比較
| パラメータ | EP910LC-40 | EP910LC44 |
|---|---|---|
| ブランド | Rochester Electronics | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $52.00 | $8.95 |
| Manufacturer | Rochester Electronics (Altera original) | Altera Corporation (now Intel PSG) |
| Device Family | Altera Classic EPLD - EP910 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 450 | — |
| Macrocells | 24 | 24 |
| Logic Array Blocks | 2 (12 macrocells each) | — |
| Propagation Delay (tPD) | 40 ns | — |
| Maximum Toggle Frequency (fMAX) | 25 MHz | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | 12 |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | — |
| パッケージ | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) | 44-pin PLCC (J-leaded) |
| Operating Temperature (Commercial) | 0 C to +70 C | — |
| Programming Method | Altera Logic Programmer (PLAD-J), 4-wire serial | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| RoHS ステータス | Not applicable (legacy) | [DATA_NEEDED: not stated in verified data] |
| Lead-Free Status | Not applicable | — |
| Product Family | — | Classic EPLD (EP910 Series) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Input Pins | — | 36 (12 dedicated + 24 I/O as inputs) |
| Global Clock Inputs | — | 2 |
| Propagation Delay (LC grade) | — | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | — | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | — | CMOS |
| 動作温度 | — | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Architecture | — | AND-OR sum-of-products with programmable macrocell feedback |
| Logic Compatibility | — | TTL-compatible CMOS I/O |