EP910LC-40 vs EP910LC44 对比

详细并排对比 EP910LC-40 出自 Rochester Electronics 和 EP910LC44 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910LC-40 EP910LC44
品牌 Rochester Electronics Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $52.00 $8.95
Manufacturer Rochester Electronics (Altera original) Altera Corporation (now Intel PSG)
Device Family Altera Classic EPLD - EP910 —
Product Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 450 —
Macrocells 24 24
Logic Array Blocks 2 (12 macrocells each) —
Propagation Delay (tPD) 40 ns —
Maximum Toggle Frequency (fMAX) 25 MHz —
User I/O Pins 36 —
Dedicated Inputs 4 12
Supply Voltage (VCC) 5 V (single supply) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS EPROM —
封装 PQCC-44 (Plastic Leaded Chip Carrier, J-lead) 44-pin PLCC (J-leaded)
Operating Temperature (Commercial) 0 C to +70 C —
Programming Method Altera Logic Programmer (PLAD-J), 4-wire serial EPROM (erasable UV for ceramic; OTP for plastic PLCC)
RoHS 状态 Not applicable (legacy) [DATA_NEEDED: not stated in verified data]
Lead-Free Status Not applicable —
Product Family — Classic EPLD (EP910 Series)
Device Type — Erasable Programmable Logic Device (EPLD)
Total Product Terms — 240
I/O Pins — 24
Total Input Pins — 36 (12 dedicated + 24 I/O as inputs)
Global Clock Inputs — 2
Propagation Delay (LC grade) — [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data]
Propagation Delay (LC-30 grade) — 33 ns (per EP910LC44-30 verified data)
Process Technology — CMOS
工作温度 — [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data]
Architecture — AND-OR sum-of-products with programmable macrocell feedback
Logic Compatibility — TTL-compatible CMOS I/O

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