EP910LI-35 vs EP910JC-30 比較
詳細な並列比較: EP910LI-35 メーカー: Altera および EP910JC-30 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LI-35 | EP910JC-30 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $25.80 | $9.75 |
| Family | Altera Classic EPLD | Classic EPLD (MAX-style) |
| Device Series | EP910 | — |
| Usable Gates | 900 | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| 電源電圧 | 5 V (4.75 V to 5.25 V) | — |
| 動作温度 | -40 °C to +85 °C (Industrial) | [DATA_NEEDED: operating temperature range] |
| パッケージ | 44-pin PLCC (J-lead) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Process Technology | CMOS EPROM | — |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| 実装タイプ | Surface Mount | Surface Mount (socket-mountable) |
| Lead Pitch | 1.27 mm | — |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Inputs | — | 36 |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EPROM, UV-erasable |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| RoHS ステータス | — | [DATA_NEEDED: RoHS compliance] |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |