EP910PC-35 vs EP910PI-35T 比較
詳細な並列比較: EP910PC-35 メーカー: Altera および EP910PI-35T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PC-35 | EP910PI-35T |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.70 | $11.15 |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | — |
| Dedicated Inputs | 12 | — |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | — |
| 電源電圧 | 5 V | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| パッケージ | 40-pin PDIP (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| 実装タイプ | Through-Hole | Through-Hole |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | UV-erasable, EPROM technology |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Usable Gates | — | 450 |
| Pin-to-Pin Logic Delay (tpd) | — | 35 ns |
| Counter Frequency (fCNT) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Process Technology | — | CMOS |
| On-board Test Circuitry | — | Yes (logic test mode for AC verification) |
| RoHS ステータス | — | [DATA_NEEDED: RoHS compliance status] |
| MSLレベル | — | [DATA_NEEDED: MSL level] |