EP910PC-35 vs EP910PI-35T Vergleich
Detaillierter Direktvergleich von EP910PC-35 von Altera und EP910PI-35T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-35 | EP910PI-35T |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,70 | $11,15 |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | — |
| Dedicated Inputs | 12 | — |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | — |
| Versorgungsspannung | 5 V | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Gehäuse | 40-pin PDIP (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Montageart | Through-Hole | Through-Hole |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | UV-erasable, EPROM technology |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Usable Gates | — | 450 |
| Pin-to-Pin Logic Delay (tpd) | — | 35 ns |
| Counter Frequency (fCNT) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Process Technology | — | CMOS |
| On-board Test Circuitry | — | Yes (logic test mode for AC verification) |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance status] |
| MSL-Level | — | [DATA_NEEDED: MSL level] |