EP910PI-15T vs EP910PI-25 比較
詳細な並列比較: EP910PI-15T メーカー: Altera および EP910PI-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PI-15T | EP910PI-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.95 | $10.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| 電源電圧 | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | — |
| パッケージ | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (Plastic DIP) |
| 実装タイプ | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| 動作温度 | [DATA_NEEDED: industrial/commercial temp range] | 0C to +70C (commercial) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| RoHS ステータス | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | Non-compliant (PDIP package) |
| Device | — | EP910 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Supply Voltage (VCC) | — | 5 V nominal |
| Process Technology | — | 5 V CMOS (EPROM-based) |
| ピン数 | — | 40 |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |