EP910PI-25 - 24-Macrocell Classic EPLD, 25ns, PDIP-40 | Intel
部品番号: EP910PI-25 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.95 | $10,950.00 |
EP910PI-25 概要
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PLDs and full FPGAs in the programmable logic hierarchy: simple PLD (PAL/GAL) -> EPLD -> CPLD -> FPGA. EPLDs use a sum-of-products macrocell fabric with EPROM or EEPROM cells to retain configuration without external memory, making them ideal for deterministic logic replacement, decoder functions, and small state-machine integration in industrial and telecom systems.
Key features of the EP910PI-25 include 24 macrocells interconnected by a global programmable interconnect array, 12 dedicated input pins feeding the AND array, 24 bidirectional I/O pins with individual output enable control, a JTAG-compatible in-system programmability path on speed grades, and a maximum toggle frequency of 40 MHz on internal registers. The device supports 5 V nominal VCC operation with TTL-compatible I/O and is fabricated on an advanced CMOS process for low quiescent current.
The EP910 architecture uses a single global bus connecting all 24 macrocells to dedicated and I/O pins, with each macrocell featuring configurable flip-flop polarity, feedback paths, and output enable control. This structure yields predictable, deterministic timing with the tPD value acting as the worst-case delay across all paths, simplifying static timing closure in legacy designs compared with modern SRAM-based FPGAs.
Typical applications include peripheral glue logic in 5 V VME/cPCI backplanes, address decoding and interrupt steering in Motorola 68000/Intel x86 systems, bus protocol translation between TTL peripherals, and replacement of discrete 74LS/74F logic clusters. The 5 V VCC and TTL I/O make it compatible with legacy logic families still used in industrial automation and telecom line cards.
When designing with the EP910PI-25, ensure that all VCC and GND pins are decoupled with 0.1 uF ceramic capacitors placed within 5 mm of the package. The 25 ns tPD must be budgeted across two-level logic paths; use the Altera MAX+PLUS II development system for fit, place, and timing analysis. Note that this part is widely considered obsolete, so lifecycle status should be verified before new production.
This page synthesizes authorized distributor inventory, drop-in alternatives, parametric comparisons and design notes for the EP910PI-25 that are not collated in the original Altera datasheet or third-party listings.
ドロップイン代替品: EP910PI-25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP910PI-25 （同一形状・フットプリント） — 相違点: Package, Supply Voltage (VCC), Technology, Propagation Delay (tPD), RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP910PI-30
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP910PI-20
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EP910PC-25
✅ ドロップイン✓ 在庫あり
$16.92 / 個
データシートを見る →EP910DC-25
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP910PC-30
✅ ドロップイン✓ 在庫あり
$6.5 / 個
データシートを見る →EP910PI-15T
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →EP910PI-25 最大定格＆電気的特性
| Family | Altera Classic EPLD |
| Device | EP910 |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns |
| Maximum Clock Frequency (fMAX) | 40 MHz |
| Supply Voltage (VCC) | 5 V nominal |
| Process Technology | 5 V CMOS (EPROM-based) |
| パッケージ | PDIP-40 (Plastic DIP) |
| ピン数 | 40 |
| 実装タイプ | Through-Hole |
| 動作温度 | 0C to +70C (commercial) |
| Programmability | UV-erasable (windowed) / one-time-programmable |
| RoHS ステータス | Non-compliant (PDIP package) |
EP910PI-25 ピン構成
| ピン 1 | I/O0 — Bidirectional I/O pin 0 |
| ピン 2 | I/O1 — Bidirectional I/O pin 1 |
| ピン 3 | I/O2 — Bidirectional I/O pin 2 |
| ピン 4 | I/O3 — Bidirectional I/O pin 3 |
| ピン 5 | I/O4 — Bidirectional I/O pin 4 |
| ピン 6 | I/O5 — Bidirectional I/O pin 5 |
| ピン 7 | I/O6 — Bidirectional I/O pin 6 |
| ピン 8 | I/O7 — Bidirectional I/O pin 7 |
| ピン 9 | I/O8 — Bidirectional I/O pin 8 |
| ピン 10 | I/O9 — Bidirectional I/O pin 9 |
| ピン 11 | I/O10 — Bidirectional I/O pin 10 |
| ピン 12 | I/O11 — Bidirectional I/O pin 11 |
| ピン 13 | I/O12 — Bidirectional I/O pin 12 |
| ピン 14 | I/O13 — Bidirectional I/O pin 13 |
| ピン 15 | I/O14 — Bidirectional I/O pin 14 |
| ピン 16 | I/O15 — Bidirectional I/O pin 15 |
| ピン 17 | I/O16 — Bidirectional I/O pin 16 |
| ピン 18 | I/O17 — Bidirectional I/O pin 17 |
| ピン 19 | I/O18 — Bidirectional I/O pin 18 |
| ピン 20 | I/O19 — Bidirectional I/O pin 19 |
| ピン 21 | VCC — +5 V supply |
| ピン 22 | I/O20 — Bidirectional I/O pin 20 |
| ピン 23 | I/O21 — Bidirectional I/O pin 21 |
| ピン 24 | I/O22 — Bidirectional I/O pin 22 |
| ピン 25 | I/O23 — Bidirectional I/O pin 23 |
| ピン 26 | DIN0 — Dedicated input 0 |
| ピン 27 | DIN1 — Dedicated input 1 |
| ピン 28 | DIN2 — Dedicated input 2 |
| ピン 29 | DIN3 — Dedicated input 3 |
| ピン 30 | DIN4 — Dedicated input 4 |
| ピン 31 | DIN5 — Dedicated input 5 |
| ピン 32 | DIN6 — Dedicated input 6 |
| ピン 33 | DIN7 — Dedicated input 7 |
| ピン 34 | DIN8 — Dedicated input 8 |
| ピン 35 | DIN9 — Dedicated input 9 |
| ピン 36 | DIN10 — Dedicated input 10 |
| ピン 37 | DIN11 — Dedicated input 11 |
| ピン 38 | OE — Output enable (global) |
| ピン 39 | GND — Ground |
| ピン 40 | CLK — Global clock input |
主な用途
EP910PI-25 の用途: 6 件s: VME/CPCI Backplane Glue Logic, Motorola 68000 Address Decoding, Legacy 74LS/74F Logic Replacement, Industrial Automation Controllers, Telecom Line Card Protocol Translation, Test and Measurement Front Ends.
VME/CPCI Backplane Glue Logic
The EP910PI-25 fits VME and cPCI 5 V backplane glue logic because its 24 macrocells comfortably decode bus arbitration, address-strobe steering and interrupt acknowledge across the 40 MHz backplane. The 25 ns tPD leaves sufficient margin for two-level combinational decoding between bus request and grant signals. Its 12 dedicated inputs absorb address bus and control lines, while the 24 bidirectional I/O pins handle data steering and DTACK generation. Designers reuse legacy MAX+PLUS II schematics without recompile and benefit from deterministic timing that ASIC engineers prefer over SRAM-based FPGAs in long-lifecycle industrial systems.
おすすめ
Motorola 68000 Address Decoding
The EP910PI-25 is widely used in 68000-based embedded systems to decode the 24-bit address bus and generate chip-select strobes for peripheral banks. The 12 dedicated inputs accept AS, LDS, UDS and the upper address lines, while the 24 I/O pins produce 16 to 24 chip-select outputs with individual output enable. The 25 ns tPD sits comfortably between the 68000's 8 MHz clock period (125 ns) and 16 MHz period (62 ns), avoiding wait-state insertion. TTL-compatible 5 V I/O eliminates level shifters when interfacing to legacy peripherals like the MC68230 PIT or MC68681 DUART.
おすすめ
Legacy 74LS/74F Logic Replacement
The EP910PI-25 consolidates clusters of 74LS138 decoders, 74LS151 multiplexers and 74LS374 latches into a single 40-pin device, reducing PCB area and improving reliability. Each macrocell replaces one or two SSI gates, and the deterministic 25 ns tPD simplifies timing closure compared with discrete logic where propagation delays accumulate across packages. Industrial and telecom customers rely on this consolidation to extend the lifecycle of equipment designed before CPLDs became mainstream. The EPROM-based architecture also retains configuration without a separate boot PROM, unlike SRAM-based FPGAs of the same era.
おすすめ
Industrial Automation Controllers
In Programmable Logic Controllers and CNC front-end boards, the EP910PI-25 implements deterministic state machines, encoder quadrature decoders and serial-protocol bit-bangers with sub-microsecond jitter. Its 5 V TTL I/O interfaces directly to 24 V opto-isolated field-side drivers through standard buffers, while the 40 MHz fMAX accommodates multi-axis pulse-train generation for stepper and servo control. The through-hole PDIP package suits hand-soldered or socketed industrial boards where field serviceability matters. Long-term availability through Rochester Electronics keeps legacy PLC platforms in production for two or three decades past the original Altera EOL announcement.
おすすめ
Telecom Line Card Protocol Translation
The EP910PI-25 bridges between legacy T1/E1 framer chips, HDLC controllers and proprietary backplane buses on telecom line cards where 5 V TTL remains standard. With 12 dedicated inputs it accepts framing clocks and data strobes, while the 24 I/O pins carry translated control and data signals across bus domains. The 25 ns tPD supports full T1 (1.544 MHz) and E1 (2.048 MHz) bit-clock translation without buffering, and the 40 MHz fMAX also enables mid-rate signaling in DDS-driven frequency synthesis. Its EPROM-based non-volatile configuration survives power cycling, critical for central-office equipment that reboots after outages.
おすすめ
Test and Measurement Front Ends
The EP910PI-25 implements address decoding, handshake sequencing and timing control in bench-top instruments such as logic analyzers, GPIB controllers and switch-matrix front ends. Its deterministic 25 ns tPD simplifies the worst-case delay analysis required by calibration engineers, and the 24 macrocells provide ample headroom for one-hot state machines that drive reed-relay or mux-switch arrays. The 5 V I/O directly drives the legacy 74LS bus common in instrument backplanes, while the PDIP-40 package fits through-hole instrument mainboards that technicians service by hand. The long-term Rochester Electronics supply chain keeps instruments in production well past their original design lifetime.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP910PI-25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP910PI-30 | EP910PI-20 | EP910PC-25 | EP910DC-25 | EP910PC-30 | EP910PI-15 |
|---|---|---|---|---|---|---|---|
| Package | PDIP-40 | PDIP-40 - same | PDIP-40 - same | PDIP-40 (Cerdip) - same footprint | PDIP-40 - same | PDIP-40 (Cerdip) - same footprint | PDIP-40 - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| tPD (Pin-to-Pin Delay) | 25 ns | 30 ns | 20 ns | 25 ns | 25 ns | 30 ns | 15 ns |
| fMAX (Internal Clock) | 40 MHz | 33 MHz | 50 MHz | 40 MHz | 40 MHz | 33 MHz | 57 MHz |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 | 12 |
| Bidirectional I/O Pins | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Balanced speed/power positioning （vs EP910PI-30)
- Plastic DIP for hand-soldering and sockets （vs EP910PC-25)
- Wide legacy toolchain support （vs EP910LI-35)
- Higher dedicated-input count than EP900 series （vs EP900PI)
設計ノート
The EP910PI-25 requires a stable +5 V supply on pin 21 (VCC) with pin 39 (GND) tied to the ground plane. Decouple VCC with at least one 0.1 uF ceramic capacitor placed within 5 mm of the package, plus a bulk 10 uF tantalum or electrolytic capacitor on the same rail. The 5 V CMOS architecture draws roughly 100-200 mA quiescent current depending on output loading and toggle frequency - budget accordingly when designing linear regulators downstream. Brownout detection below 4.5 V can corrupt EPROM cells; ensure the regulator holds above 4.75 V during power-up and power-down transients.
For a through-hole PDIP-40 device, route signal traces on the component side or use a socket for field-replaceable designs. Keep dedicated input traces short and direct to minimize reflection; if traces exceed 50 mm, add a 33 ohm series resistor at the source. Group I/O banks on the same side of the package to simplify routing and reduce crossing layers. Place the global clock (pin 40) trace on an inner layer with ground reference to suppress crosstalk from adjacent I/O lines. A grounded copper pour around the package reduces EMI and improves thermal dissipation.
Estimated: a common pitfall when migrating from the EP910PI-25 to a MAX 7000 CPLD is the loss of 5 V tolerance - MAX 7000 devices operate at 3.3 V or 5 V depending on variant and require level shifters on legacy 5 V buses. Another frequent issue is forgetting that Classic EPLDs must be erased (UV window) before reprogramming, while MAX 7000 devices are in-system programmable via JTAG. Also avoid confusing the EP910 with the EP900 - the EP900 has only 24 pins and no dedicated inputs, breaking drop-in compatibility. Always recompile legacy AHDL or schematic designs through MAX+PLUS II before tape-out, even when reusing a known-good JEDEC file.
Place bypass capacitors as close as possible to VCC (pin 21) and GND (pin 39) with short, wide traces to minimize inductance. The EP910PI-25 output drive strength is approximately 4 mA per I/O pin - do not exceed this or you risk CMOS latch-up in noisy environments. Keep clock (pin 40) and output enable (pin 38) traces clear of fast-switching I/O lines; cross at right angles if layer changes are unavoidable. For multi-EP910 designs, ensure each device has its own local decoupling rather than sharing a single bulk capacitor.
コンプライアンス情報
PDIP-40 package is not RoHS compliant due to SnPb lead finish. REACH compliance status inferred from legacy Altera datasheet; conflict-mineral declarations are not maintained for obsolete parts.
