EP910PI-25 vs EP910PI-15T 比較
詳細な並列比較: EP910PI-25 メーカー: Intel および EP910PI-15T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PI-25 | EP910PI-15T |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.95 | $10.95 |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Device | EP910 | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Process Technology | 5 V CMOS (EPROM-based) | — |
| パッケージ | PDIP-40 (Plastic DIP) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| ピン数 | 40 | — |
| 実装タイプ | Through-Hole | Through-Hole |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: industrial/commercial temp range] |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| RoHS ステータス | Non-compliant (PDIP package) | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| 電源電圧 | — | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | — | 15 ns max (speed grade -15) |
| Technology | — | CMOS EEPROM (electrically erasable) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | — | JEDEC-standard, serial/parallel programmer |