EPC27C32N vs EPC21LC20 比較

詳細な並列比較: EPC27C32N メーカー: Altera および EPC21LC20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPC27C32N EPC21LC20
ブランド Altera Intel
カテゴリ FPGA & CPLD Memory ICs
ライフサイクル状態 Obsolete 有効
在庫状況 In Stock In Stock
単価(USD) $9.95 $10.40
メモリタイプ Configuration EPROM (non-volatile) Serial Configuration PROM (Flash-based, in-system programmable)
Density 32 Mbit 2 Mb (2,097,152 bits)
Configuration Interface Serial (Altera Passive Serial / Active Serial / JTAG) —
電源電圧 [DATA_NEEDED: VCC nominal] —
Supply Voltage Range [DATA_NEEDED: VCC min/max] —
Programmability In-system programmable (IEEE 1532 / JTAG) —
パッケージ PLCC-20 —
Package Code Suffix N = PLCC-20 —
実装タイプ Surface Mount (PLCC) Surface Mount (PLCC socket or solder)
動作温度 [DATA_NEEDED: industrial/commercial] —
Multi-device Daisy-chain Yes (page-mode supported) —
Reconfiguration Software-controllable / on-the-fly via JTAG —
RoHS ステータス [DATA_NEEDED: depends on date code; older N suffix often Pb-free] [DATA_NEEDED: confirm from Altera product page]
Lead-free [DATA_NEEDED] —
Family EPC Enhanced Configuration Device —
Compatible FPGA Targets Altera Stratix, Cyclone, Arria, FLEX, ACEX series —
Manufacturer Intel (formerly Altera) —
Configuration Mode Supported — Serial (PS) for Altera SRAM-based LUT FPGAs
Maximum DCLK Frequency — 10 MHz
Access Time — approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure]
Programming Interface — IEEE 1149.1 (JTAG)
Program/Erase Endurance — 100 cycles minimum [DATA_NEEDED: confirm from datasheet]
Operating Voltage (VCC) — 3.0 V to 3.6 V (3.3 V typical)
Standby Current — [DATA_NEEDED: ICCSB value]
Active Read Current — [DATA_NEEDED: ICC active current]
Operating Temperature (commercial) — 0 °C to +70 °C (LC suffix)
Operating Temperature (industrial) — [DATA_NEEDED: -40 to +85 °C for LI variant]
パッケージ / ケース — 20-pin PLCC (J-lead, JEDEC MS-018)
MSLレベル — [DATA_NEEDED: confirm moisture sensitivity level]
Lead-Free (Pb-free) — [DATA_NEEDED: confirm]
Compatible FPGA Families — ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT)
JTAG Boundary-Scan Compliant — Yes (IEEE Std 1149.1)
Data Width — 1 bit (serial DATA output)

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