EPC27C32N vs EPC21LC20 对比
详细并排对比 EPC27C32N 出自 Altera 和 EPC21LC20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC27C32N | EPC21LC20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | Memory ICs |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $10.40 |
| 存储器类型 | Configuration EPROM (non-volatile) | Serial Configuration PROM (Flash-based, in-system programmable) |
| Density | 32 Mbit | 2 Mb (2,097,152 bits) |
| Configuration Interface | Serial (Altera Passive Serial / Active Serial / JTAG) | — |
| 电源电压 | [DATA_NEEDED: VCC nominal] | — |
| Supply Voltage Range | [DATA_NEEDED: VCC min/max] | — |
| Programmability | In-system programmable (IEEE 1532 / JTAG) | — |
| 封装 | PLCC-20 | — |
| Package Code Suffix | N = PLCC-20 | — |
| 安装类型 | Surface Mount (PLCC) | Surface Mount (PLCC socket or solder) |
| 工作温度 | [DATA_NEEDED: industrial/commercial] | — |
| Multi-device Daisy-chain | Yes (page-mode supported) | — |
| Reconfiguration | Software-controllable / on-the-fly via JTAG | — |
| RoHS 状态 | [DATA_NEEDED: depends on date code; older N suffix often Pb-free] | [DATA_NEEDED: confirm from Altera product page] |
| Lead-free | [DATA_NEEDED] | — |
| Family | EPC Enhanced Configuration Device | — |
| Compatible FPGA Targets | Altera Stratix, Cyclone, Arria, FLEX, ACEX series | — |
| Manufacturer | Intel (formerly Altera) | — |
| Configuration Mode Supported | — | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | — | 10 MHz |
| Access Time | — | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Programming Interface | — | IEEE 1149.1 (JTAG) |
| Program/Erase Endurance | — | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | — | [DATA_NEEDED: ICCSB value] |
| Active Read Current | — | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | — | 0 °C to +70 °C (LC suffix) |
| Operating Temperature (industrial) | — | [DATA_NEEDED: -40 to +85 °C for LI variant] |
| 封装 / 外壳 | — | 20-pin PLCC (J-lead, JEDEC MS-018) |
| MSL 等级 | — | [DATA_NEEDED: confirm moisture sensitivity level] |
| Lead-Free (Pb-free) | — | [DATA_NEEDED: confirm] |
| Compatible FPGA Families | — | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | — | Yes (IEEE Std 1149.1) |
| Data Width | — | 1 bit (serial DATA output) |