EPC2LC20EM vs EPC2LC20 比較
詳細な並列比較: EPC2LC20EM メーカー: Intel および EPC2LC20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC2LC20EM | EPC2LC20 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | Memory ICs |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.95 | $7.20 |
| メモリタイプ | Serial Configuration Memory (EPC2 family) | Non-volatile configuration PROM |
| Density | 1.6 Mbit | — |
| インターフェース | Serial / Parallel configuration, JTAG ISP | — |
| Operating Voltage (Core) | 3.3 V | — |
| Programming Mode | In-system programmable via JTAG (IEEE 1149.1) | — |
| Package Type | PLCC-20 (plastic) | — |
| 動作温度 | -40C to +85C (industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| RoHS ステータス | [DATA_NEEDED: lead-free / RoHS classification] | Non-Compliant (original Altera Pb-containing part) |
| Configuration Compatibility | Stratix, Cyclone, APEX, ACEX, FLEX, MAX, Excalibur, HardCopy | — |
| Data Retention | [DATA_NEEDED: minimum data-retention years] | — |
| Program/Erase Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| Access Time | [DATA_NEEDED: tOE / tAA in ns] | — |
| 実装タイプ | Surface Mount (PLCC socket or solder) | Surface Mount |
| MSLレベル | [DATA_NEEDED: moisture sensitivity level] | — |
| Manufacturer Family | EPC2 Enhanced Configuration Device | — |
| メモリサイズ | — | 1.6 Mbit |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| パッケージ | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |