EPC4QC1C00N vs EPC4QC100TQ 比較
詳細な並列比較: EPC4QC1C00N メーカー: Altera および EPC4QC100TQ メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC4QC1C00N | EPC4QC100TQ |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | Memory ICs |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.10 | $14.95 |
| Device Family | Enhanced Configuration Device (EPC4) | — |
| Memory Density | 4 Mbit (4,194,304 bits) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage Tolerance | 3.3 V / 5 V tolerant | — |
| Interface to FPGA | Serial DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE | — |
| Configuration Data Width | 4-bit multiplexed on single DATA pin | — |
| パッケージ | 100-pin PQFP (QFP-100) | 100-pin TQFP (TQ) 20x14 mm |
| 動作温度 | -40 C to +85 C (industrial) | -40C to +85C |
| In-System Programming | JTAG (IEEE 1149.1) | — |
| Programming Voltage | On-chip generated, no external VPP | — |
| Page Mode | Yes, multi-page storage supported | — |
| Target FPGA Families | Stratix, Cyclone, APEX, Mercury, ACEX | — |
| Configuration Clock (DCLK) | [DATA_NEEDED: DCLK max frequency] | — |
| MSLレベル | 3 (per JEDEC J-STD-020) | 3 (168 hours) |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status not in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| メモリタイプ | — | Flash configuration PROM |
| メモリサイズ | — | 4 Mbit |
| Configuration Modes | — | Passive Serial (PS), JTAG |
| Maximum Configuration Clock | — | 66 MHz |
| 電源電圧 | — | 3.3 V typical (5.0 V tolerant I/O) |
| インターフェース | — | Serial configuration data, JTAG boundary scan |
| 実装タイプ | — | Surface Mount |
| Compression Support | — | Yes (Altera proprietary) |
| In-System Programmable | — | Yes |
| Compatible FPGA Families | — | Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K |
| Lead Free | — | [DATA_NEEDED: lead-free status not in verified data] |