EPC4QC1C00N vs EPC4QC100TQ 对比

详细并排对比 EPC4QC1C00N 出自 Altera 和 EPC4QC100TQ 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC4QC1C00N EPC4QC100TQ
品牌 Altera Altera
分类 FPGA & CPLD Memory ICs
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.10 $14.95
Device Family Enhanced Configuration Device (EPC4) —
Memory Density 4 Mbit (4,194,304 bits) —
Supply Voltage (VCC) 3.0 V to 3.6 V (3.3 V typical) —
I/O Voltage Tolerance 3.3 V / 5 V tolerant —
Interface to FPGA Serial DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE —
Configuration Data Width 4-bit multiplexed on single DATA pin —
封装 100-pin PQFP (QFP-100) 100-pin TQFP (TQ) 20x14 mm
工作温度 -40 C to +85 C (industrial) -40C to +85C
In-System Programming JTAG (IEEE 1149.1) —
Programming Voltage On-chip generated, no external VPP —
Page Mode Yes, multi-page storage supported —
Target FPGA Families Stratix, Cyclone, APEX, Mercury, ACEX —
Configuration Clock (DCLK) [DATA_NEEDED: DCLK max frequency] —
MSL 等级 3 (per JEDEC J-STD-020) 3 (168 hours)
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status not in verified data]
Lead-Free [DATA_NEEDED: lead-free status] —
存储器类型 — Flash configuration PROM
存储容量 — 4 Mbit
Configuration Modes — Passive Serial (PS), JTAG
Maximum Configuration Clock — 66 MHz
电源电压 — 3.3 V typical (5.0 V tolerant I/O)
接口 — Serial configuration data, JTAG boundary scan
安装类型 — Surface Mount
Compression Support — Yes (Altera proprietary)
In-System Programmable — Yes
Compatible FPGA Families — Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Lead Free — [DATA_NEEDED: lead-free status not in verified data]

数据手册与资源

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