EPC81500RC304-3 vs EPC4QC100N 比較
詳細な並列比較: EPC81500RC304-3 メーカー: Altera および EPC4QC100N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPC81500RC304-3 - Enhanced Configuration Device for SRAM FPGAs | Altera
EPC81500RC304-3 Obsolete
仕様比較
| パラメータ | EPC81500RC304-3 | EPC4QC100N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | Memory ICs |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $23.90 | $8.10 |
| Device Type | Enhanced Configuration Device (Flash-based FPGA configuration memory) | — |
| Target FPGA Families | Altera FLEX 8000, FLEX 10K, ACEX 1K, APEX series SRAM-based LUT FPGAs | — |
| Configuration Memory Size | 8 Mbit | — |
| Interface Modes | Parallel-byte and serial bitstream modes | — |
| Programming Interface | JTAG (IEEE 1149.1) and byte-wide parallel | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Voltage VCCIO | 3.3 V or 5.0 V tolerant | — |
| 動作温度範囲 | 0 C to +70 C (commercial) | — |
| パッケージ | 304-pin PQFP (RC304) | 100-pin PQFP (Plastic Quad Flat Pack) |
| 実装タイプ | Surface Mount | Surface Mount |
| ピン数 | 304 | — |
| Configuration Clock | DCLK generated internally or externally to target FPGA | — |
| Multi-Device Support | Yes - daisy-chain configuration of multiple FPGAs | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| メモリタイプ | — | Flash (NOR, configuration PROM) |
| メモリサイズ | — | 4 Mbit (4,194,304 bits) |
| Programmable Type | — | In System Programmable (ISP) |
| Configuration Interface | — | Serial / Parallel / JTAG (IEEE 1149.1) |
| Maximum DCLK Frequency | — | 66.7 MHz |
| On-Chip Decompression | — | Yes |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Typical Supply Voltage | — | 3.3 V |
| 動作温度 | — | 0 C to 70 C (commercial) |
| Package Dimensions | — | 20 x 14 mm |
| Pin Pitch | — | 0.65 mm |
| Packaging | — | Tray |
| Lead Free / RoHS | — | Yes (per chipdig datasheet excerpt) |
| Family | — | EPC4 Enhanced Configuration Device |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |