EPC8820ARC208-3N vs EPC81500RC304-3 比較
詳細な並列比較: EPC8820ARC208-3N メーカー: Altera および EPC81500RC304-3 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPC81500RC304-3 - Enhanced Configuration Device for SRAM FPGAs | Altera
EPC81500RC304-3 Obsolete仕様比較
| パラメータ | EPC8820ARC208-3N | EPC81500RC304-3 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.25 | $23.90 |
| Family | FLEX 8000 | — |
| Device Type | SRAM-based Programmable Logic Device (PLD) | Enhanced Configuration Device (Flash-based FPGA configuration memory) |
| Usable Gates | 8,000 | — |
| Logic Cells / Logic Elements (LEs) | 672 | — |
| Maximum User I/O | 152 | — |
| Maximum Operating Frequency | 125 MHz | — |
| Propagation Delay (tpd) | 5.0 ns | — |
| Process Technology | 0.42 µm CMOS | — |
| Core Supply Voltage (VCCINT) | 5.0 V nominal (4.75 V to 5.25 V) | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V (programmable I/O standard) | — |
| Operating Temperature Grade | Industrial (N suffix) | — |
| Configuration Method | SRAM, loaded via external EPROM or Altera serial configuration device (EPC1 / EPC1064 / EPC1213 / EPC1441) | — |
| パッケージ | 208-pin RQFP (Plastic Quad Flat Pack) | 304-pin PQFP (RC304) |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | unknown | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Configuration Device Compatibility | EPC1, EPC1064, EPC1213, EPC1441 (per manufacturer datasheet) | — |
| Target FPGA Families | — | Altera FLEX 8000, FLEX 10K, ACEX 1K, APEX series SRAM-based LUT FPGAs |
| Configuration Memory Size | — | 8 Mbit |
| Interface Modes | — | Parallel-byte and serial bitstream modes |
| Programming Interface | — | JTAG (IEEE 1149.1) and byte-wide parallel |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage VCCIO | — | 3.3 V or 5.0 V tolerant |
| 動作温度範囲 | — | 0 C to +70 C (commercial) |
| ピン数 | — | 304 |
| Configuration Clock | — | DCLK generated internally or externally to target FPGA |
| Multi-Device Support | — | Yes - daisy-chain configuration of multiple FPGAs |