EPC8820ARC208-3N vs EPC81500RC304-3 비교
다음의 상세 나란히 비교: EPC8820ARC208-3N 제조: Altera 및 EPC81500RC304-3 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPC81500RC304-3 - Enhanced Configuration Device for SRAM FPGAs | Altera
EPC81500RC304-3 Obsolete사양 비교
| 파라미터 | EPC8820ARC208-3N | EPC81500RC304-3 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $21.25 | $23.90 |
| Family | FLEX 8000 | — |
| Device Type | SRAM-based Programmable Logic Device (PLD) | Enhanced Configuration Device (Flash-based FPGA configuration memory) |
| Usable Gates | 8,000 | — |
| Logic Cells / Logic Elements (LEs) | 672 | — |
| Maximum User I/O | 152 | — |
| Maximum Operating Frequency | 125 MHz | — |
| Propagation Delay (tpd) | 5.0 ns | — |
| Process Technology | 0.42 µm CMOS | — |
| Core Supply Voltage (VCCINT) | 5.0 V nominal (4.75 V to 5.25 V) | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V (programmable I/O standard) | — |
| Operating Temperature Grade | Industrial (N suffix) | — |
| Configuration Method | SRAM, loaded via external EPROM or Altera serial configuration device (EPC1 / EPC1064 / EPC1213 / EPC1441) | — |
| 패키지 | 208-pin RQFP (Plastic Quad Flat Pack) | 304-pin PQFP (RC304) |
| 실장 유형 | Surface Mount | Surface Mount |
| RoHS 상태 | unknown | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Configuration Device Compatibility | EPC1, EPC1064, EPC1213, EPC1441 (per manufacturer datasheet) | — |
| Target FPGA Families | — | Altera FLEX 8000, FLEX 10K, ACEX 1K, APEX series SRAM-based LUT FPGAs |
| Configuration Memory Size | — | 8 Mbit |
| Interface Modes | — | Parallel-byte and serial bitstream modes |
| Programming Interface | — | JTAG (IEEE 1149.1) and byte-wide parallel |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage VCCIO | — | 3.3 V or 5.0 V tolerant |
| 동작 온도 범위 | — | 0 C to +70 C (commercial) |
| 핀 수 | — | 304 |
| Configuration Clock | — | DCLK generated internally or externally to target FPGA |
| Multi-Device Support | — | Yes - daisy-chain configuration of multiple FPGAs |