EPF10K200SFI672-2 vs EPF10K200SFC672-2 比較
詳細な並列比較: EPF10K200SFI672-2 メーカー: Intel および EPF10K200SFC672-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPF10K200SFI672-2 | EPF10K200SFC672-2 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $99.50 | $320.00 |
| Family | FLEX 10KE | — |
| Logic Elements | 9984 | 9,984 |
| System Gates | 200000 | 200,000 |
| Logic Array Blocks (LABs) | 1248 | 1,248 |
| User I/Os | 470 | — |
| Embedded Array Blocks (EABs) | 24 | — |
| Embedded Memory (EAB SRAM) | 96 Kbit | — |
| Distributed Memory | 98304 bits | — |
| Process Technology | 0.22 µm (Arrow lists 0.42 µm) | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V (2.375 V to 2.625 V) |
| パッケージ | 672-pin FineLine BGA (FBGA) | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch |
| Speed Grade | -2 | -2 |
| 動作温度 | Industrial (-40C to +85C) | 0 °C to +70 °C (Commercial) |
| JTAG Boundary Scan | IEEE Std. 1149.1-1990 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (3.3 V, 33/66 MHz) on -1 speed grade | — |
| Programming | SRAM-based, in-system programmable | — |
| RoHS ステータス | Not compliant (per Arrow EU RoHS listing) | [DATA_NEEDED: RoHS compliance status] |
| Series | — | FLEX 10KE |
| User I/O Pins | — | 470 |
| Embedded Memory (bits) | — | 98,304 |
| I/O Supply Voltage | — | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Internal Propagation Delay | — | 0.4 ns |
| Maximum Operating Frequency | — | 200 MHz |
| Configuration Method | — | SRAM-based, passive parallel asynchronous |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| On-chip PLL | — | Yes |