EPF10K200SRC240-1 vs EPF10K200SRC240-3N 比較
詳細な並列比較: EPF10K200SRC240-1 メーカー: Intel および EPF10K200SRC240-3N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPF10K200SRC240-1 | EPF10K200SRC240-3N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $112.00 | $162.00 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | FLEX-10KS | — |
| Family | FLEX 10K Embedded Programmable Logic | FLEX 10KE |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Number of Logic Elements | 9984 | — |
| Number of LABs (Logic Array Blocks) | 1248 | — |
| Number of EABs (Embedded Array Blocks) | 24 | — |
| Total EAB RAM Bits | 40960 | — |
| Total SRAM Bits | 98304 | — |
| Typical System Gates | 200000 | 200,000 |
| Maximum System Gates | 513000 | — |
| Number of I/O Pins | 182 | — |
| Supply Voltage - Core | 5.0 V | — |
| Supply Voltage - I/O | 3.3 V / 5.0 V (multiVolt) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | -40C to +85C (industrial) | 0 °C to +70 °C (Commercial) |
| パッケージ / ケース | 240-BFQFP Exposed Pad (RQFP-240) | — |
| Supplier Device Package | 240-RQFP (32x32 mm) | — |
| Speed Grade | -1 (fastest) | -3 (commercial) |
| Programmability | SRAM-based, in-system via JTAG | — |
| JTAG (IEEE 1149.1) | Yes | — |
| RoHS ステータス | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements (LEs) | — | 9,984 |
| Maximum Logic Elements | — | 9,984 |
| Embedded Array Blocks (EABs) | — | 24 |
| Maximum User RAM Bits | — | 98,304 |
| Logic Array Blocks (LABs) | — | 1,248 |
| User I/Os | — | 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions |
| Propagation Delay (tPD) | — | 0.40 ns |
| Internal Operating Frequency | — | 166.67 MHz |
| Process Technology | — | 0.22 µm CMOS SRAM |
| Core Supply Voltage | — | 2.5 V |
| MultiVolt I/O Support | — | 2.5 V and 3.3 V interfaces |
| パッケージ | — | 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic) |
| Configuration Method | — | SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading |