EPF10K200SRC240-1 vs EPF10K200SRC240-3N Comparação

Comparação detalhada lado a lado de EPF10K200SRC240-1 por Intel e EPF10K200SRC240-3N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EPF10K200SRC240-1 EPF10K200SRC240-3N
Marca Intel Intel
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida NRND Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $112,00 $162,00
Manufacturer Intel (formerly Altera) —
Series FLEX-10KS —
Family FLEX 10K Embedded Programmable Logic FLEX 10KE
Device Type FPGA - Field Programmable Gate Array —
Number of Logic Elements 9984 —
Number of LABs (Logic Array Blocks) 1248 —
Number of EABs (Embedded Array Blocks) 24 —
Total EAB RAM Bits 40960 —
Total SRAM Bits 98304 —
Typical System Gates 200000 200,000
Maximum System Gates 513000 —
Number of I/O Pins 182 —
Supply Voltage - Core 5.0 V —
Supply Voltage - I/O 3.3 V / 5.0 V (multiVolt) —
Tipo de montagem Surface Mount Surface Mount
Temperatura de operação -40C to +85C (industrial) 0 °C to +70 °C (Commercial)
Encapsulamento / Caixa 240-BFQFP Exposed Pad (RQFP-240) —
Supplier Device Package 240-RQFP (32x32 mm) —
Speed Grade -1 (fastest) -3 (commercial)
Programmability SRAM-based, in-system via JTAG —
JTAG (IEEE 1149.1) Yes —
Status RoHS [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Logic Elements (LEs) — 9,984
Maximum Logic Elements — 9,984
Embedded Array Blocks (EABs) — 24
Maximum User RAM Bits — 98,304
Logic Array Blocks (LABs) — 1,248
User I/Os — 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions
Propagation Delay (tPD) — 0.40 ns
Internal Operating Frequency — 166.67 MHz
Process Technology — 0.22 µm CMOS SRAM
Core Supply Voltage — 2.5 V
MultiVolt I/O Support — 2.5 V and 3.3 V interfaces
Encapsulamento — 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch
JTAG Support — IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic)
Configuration Method — SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading

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