EPF10K200SRC240-3N vs EPF10K200SRC240-2 比較
詳細な並列比較: EPF10K200SRC240-3N メーカー: Intel および EPF10K200SRC240-2 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPF10K200SRC240-3N | EPF10K200SRC240-2 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $162.00 | $62.50 |
| Family | FLEX 10KE | FLEX 10KS (FLEX 10KE/10KA generation) |
| Typical System Gates | 200,000 | — |
| Logic Elements (LEs) | 9,984 | — |
| Maximum Logic Elements | 9,984 | — |
| Embedded Array Blocks (EABs) | 24 | — |
| Maximum User RAM Bits | 98,304 | — |
| Logic Array Blocks (LABs) | 1,248 | — |
| User I/Os | 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions | — |
| Propagation Delay (tPD) | 0.40 ns | — |
| Internal Operating Frequency | 166.67 MHz | — |
| Process Technology | 0.22 µm CMOS SRAM | 0.42 micrometer CMOS SRAM |
| Core Supply Voltage | 2.5 V | 2.375 V to 2.625 V (nominal 2.5 V) |
| MultiVolt I/O Support | 2.5 V and 3.3 V interfaces | — |
| 動作温度 | 0 °C to +70 °C (Commercial) | 0C to +70C (Commercial, TA) |
| パッケージ | 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch | — |
| 実装タイプ | Surface Mount | Surface Mount |
| JTAG Support | IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic) | — |
| Configuration Method | SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | -3 (commercial) | -2 (~80 MHz internal, typical) |
| Series | — | FLEX 10KS |
| Number of Logic Elements (LEs) | — | 9984 |
| Number of Logic Array Blocks (LABs) | — | 1248 |
| Total RAM Bits | — | 98304 |
| Number of User I/Os | — | 182 |
| Number of Gates | — | 513000 |
| パッケージ / ケース | — | 240-BFQFP Exposed Pad (240-RQFP, 32x32 mm) |
| Terminal Form | — | GULL WING |
| Number of Terminals | — | 240 |
| Configuration Interface | — | IEEE 1149.1 JTAG + Altera EPC EEPROM |