EPM240T100C3N vs EPM240T100I3N 比較
詳細な並列比較: EPM240T100C3N メーカー: Altera および EPM240T100I3N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM240T100I3N - 192-Macrocell MAX II CPLD, 100-TQFP, Industrial | Intel
EPM240T100I3N ⚠ ラストタイムバイ仕様比較
| パラメータ | EPM240T100C3N | EPM240T100I3N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.05 | $5.45 |
| Series | MAX II | — |
| Device Family | MAX II CPLD (EPM240) | — |
| Logic Elements (LE) | 240 | — |
| Macrocells | 192 | — |
| User I/O Pins | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| パッケージ | 100-pin TQFP (14x14 mm) | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch |
| Configuration Memory | Internal Flash (non-volatile) | — |
| Pin-to-Pin Logic Delay (tPD) | 4.4 ns (typical) | — |
| Maximum Operating Frequency | 200 MHz (internal oscillator) | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG / IEEE 1149.1 ISP |
| 動作温度 | 0 °C to +85 °C (commercial) | — |
| Quiescent Current (typical) | 35 mA | — |
| RoHS ステータス | Compliant | Compliant |
| 実装タイプ | Surface Mount | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020) |
| Family | — | MAX II |
| Device Logic Elements / Macrocells | — | 192 macrocells |
| Maximum User I/O Pins | — | 80 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| On-chip User Flash Memory | — | 8 Kbits |
| Internal Performance | — | 304 MHz |
| Pin-to-pin Logic Delay (tPD1) | — | 4.6 ns |
| Global Clock Networks | — | 4 |
| Technology Node | — | 0.18 um, 6-layer-metal flash CMOS |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| MultiVolt I/O Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| 動作接合温度 | — | -40C to +100C (industrial, 'I' grade) |
| Speed Grade | — | 3 |
| Instant-on (non-volatile) | — | Yes (flash-based) |