EPM240T100C3N vs EPM240T100I3N 비교
다음의 상세 나란히 비교: EPM240T100C3N 제조: Altera 및 EPM240T100I3N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM240T100C3N | EPM240T100I3N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.05 | $5.45 |
| Series | MAX II | — |
| Device Family | MAX II CPLD (EPM240) | — |
| Logic Elements (LE) | 240 | — |
| Macrocells | 192 | — |
| User I/O Pins | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| 패키지 | 100-pin TQFP (14x14 mm) | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch |
| Configuration Memory | Internal Flash (non-volatile) | — |
| Pin-to-Pin Logic Delay (tPD) | 4.4 ns (typical) | — |
| Maximum Operating Frequency | 200 MHz (internal oscillator) | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG / IEEE 1149.1 ISP |
| 동작 온도 | 0 °C to +85 °C (commercial) | — |
| Quiescent Current (typical) | 35 mA | — |
| RoHS 상태 | Compliant | Compliant |
| 실장 유형 | Surface Mount | — |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020) |
| Family | — | MAX II |
| Device Logic Elements / Macrocells | — | 192 macrocells |
| Maximum User I/O Pins | — | 80 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| On-chip User Flash Memory | — | 8 Kbits |
| Internal Performance | — | 304 MHz |
| Pin-to-pin Logic Delay (tPD1) | — | 4.6 ns |
| Global Clock Networks | — | 4 |
| Technology Node | — | 0.18 um, 6-layer-metal flash CMOS |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| MultiVolt I/O Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| 동작 접합 온도 | — | -40C to +100C (industrial, 'I' grade) |
| Speed Grade | — | 3 |
| Instant-on (non-volatile) | — | Yes (flash-based) |