EPM3032ALC44-4N vs EPM3032ALC44-7N 比較
詳細な並列比較: EPM3032ALC44-4N メーカー: Intel および EPM3032ALC44-7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3032ALC44-4N | EPM3032ALC44-7N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1.32 | $1.05 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 32 | — |
| Logic Array Blocks (LABs) | 2 | — |
| Usable Gates | 600 | — |
| User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns | — |
| Maximum Counter Frequency (fCNT) | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| パッケージ | 44-pin PLCC (J-Lead) | 44-PLCC (J-Lead, 16.59 x 16.59 mm) |
| 実装タイプ | Surface Mount | Surface Mount (PLCC socket compatible) |
| Programmability | EEPROM (non-volatile), IEEE 1149.1 JTAG ISP, IEEE 1532 compliant | — |
| 動作温度 | [DATA_NEEDED: industrial/commercial grade] | 0C to +70C (commercial grade) |
| RoHS ステータス | [DATA_NEEDED: from datasheet] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Altera (Intel) |
| Series | — | MAX 3000A |
| Macro Cells | — | 32 |
| Logic Gates | — | 600 usable gates |
| Propagation Delay (tPD1) | — | 7.5 ns (max, pin-to-pin) |
| Internal Counter Frequency (fCNT) | — | 227.3 MHz (max) |
| Number of Logic Elements / Blocks | — | 2 LABs (16 macrocells each) |
| Number of I/O Pins | — | 34 usable I/O (44 total package pins) |
| Number of Dedicated Inputs | — | 4 |
| Programmable Type | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| メモリタイプ | — | EEPROM (non-volatile, 100 program/erase cycles) |
| Supply Voltage - Internal (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Bank Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| MSLレベル | — | 3 (168 hours) |
| Process Technology | — | CMOS EEPROM |