EPM3064AT100-10N vs EPM3064ATI44-10N 比較
詳細な並列比較: EPM3064AT100-10N メーカー: Altera および EPM3064ATI44-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3064AT100-10N | EPM3064ATI44-10N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.45 | $3.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1,250 | 1250 |
| User I/O Pins | 66 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Bank Voltage | 3.3 V | — |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | — |
| パッケージ | TQFP-100 (T100), 14 mm x 14 mm | 44-pin TQFP |
| Operating Temperature (Commercial) | 0C to +70C | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | Non-Compliant (per digchip datasheet excerpt) |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 34 |
| Dedicated Inputs | — | 4 |
| Logic Blocks | — | 4 |
| Pin-to-Pin Delay | — | 10 ns (-10 speed grade) |
| Maximum Frequency (fMAX) | — | 100 MHz |
| Programmable Type | — | In-System Programmable (EEPROM) |
| ISP Interface | — | IEEE Std. 1149.1 (JTAG) |
| ISP Standard Compliance | — | IEEE Std. 1532 |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V (MultiVolt) |
| 動作温度 | — | -40C to +85C (Industrial, "N" suffix) |
| Process Technology | — | CMOS EEPROM |
| Boundary-Scan Test | — | Built-in (JTAG) |
| 実装タイプ | — | Surface Mount |
| Lead-Free Status | — | Contains Lead (per digchip datasheet excerpt) |