EPM3064AT100-10N vs EPM3064ATI44-10N Comparison
Detailed side-by-side comparison of EPM3064AT100-10N by Altera and EPM3064ATI44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3064AT100-10N | EPM3064ATI44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.45 | $3.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | β |
| Usable Gates | 1,250 | 1250 |
| User I/O Pins | 66 | β |
| Speed Grade | -10 (10 ns pin-to-pin delay) | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Bank Voltage | 3.3 V | β |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | β |
| ISP Compliance | IEEE Std. 1532 | β |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | β |
| Package | TQFP-100 (T100), 14 mm x 14 mm | 44-pin TQFP |
| Operating Temperature (Commercial) | 0C to +70C | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Non-Compliant (per digchip datasheet excerpt) |
| Lead-Free | [DATA_NEEDED: lead-free finish] | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| User I/Os | β | 34 |
| Dedicated Inputs | β | 4 |
| Logic Blocks | β | 4 |
| Pin-to-Pin Delay | β | 10 ns (-10 speed grade) |
| Maximum Frequency (fMAX) | β | 100 MHz |
| Programmable Type | β | In-System Programmable (EEPROM) |
| ISP Interface | β | IEEE Std. 1149.1 (JTAG) |
| ISP Standard Compliance | β | IEEE Std. 1532 |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 2.5 V (MultiVolt) |
| Operating Temperature | β | -40C to +85C (Industrial, "N" suffix) |
| Process Technology | β | CMOS EEPROM |
| Boundary-Scan Test | β | Built-in (JTAG) |
| Mounting Type | β | Surface Mount |
| Lead-Free Status | β | Contains Lead (per digchip datasheet excerpt) |