EPM3128ATC100-10N vs EPM3128ATC100-10NS 比較
詳細な並列比較: EPM3128ATC100-10N メーカー: Altera および EPM3128ATC100-10NS メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N Nrnd仕様比較
| パラメータ | EPM3128ATC100-10N | EPM3128ATC100-10NS |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.20 | $6.50 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2500 | — |
| Number of I/O | 80 | — |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fMAX) | 98 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | — |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | EEPROM (non-volatile) |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | — |
| パッケージ | 100-pin TQFP (14 x 14 x 1.0 mm) | TQFP-100 |
| 動作温度 | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | Yes | [DATA_NEEDED: lead-free status] |
| MSLレベル | 3 (per JEDEC J-STD-020) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 80 |
| ピン数 | — | 100 |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 3.3 V or 2.5 V (5.0 V-tolerant inputs) |
| Logic-Level Compatibility | — | 5.0 V, 3.3 V, 2.5 V |
| Programmability | — | In-system (ISP), IEEE Std. 1532 |
| Boundary Scan | — | IEEE 1149.1 JTAG |