EPM3128ATC100-10NS - MAX 3000A CPLD, 128 Macro, 100-TQFP | Intel
部品番号: EPM3128ATC100-10NS ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $10.13 | $10.13 |
| 10 | $9.2 | $92.00 |
| 100 | $8.1 | $810.00 |
| 500 | $7.3 | $3,650.00 |
| 1,000 | $6.5 | $6,500.00 |
EPM3128ATC100-10NS 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macro-cell arrays with a programmable interconnect matrix. It sits between simple logic gates and FPGAs in the programmable logic hierarchy and is widely used for glue logic, bus interfacing, state-machine control, and power-up sequencing in digital systems. The MAX 3000A family belongs to Intel's (formerly Altera's) classic CPLD portfolio, providing instant-on, deterministic timing, and high pin-to-pin speed that FPGAs cannot match for small, fast, fixed-function blocks.
Key features of the EPM3128ATC100-10NS include 4.5 ns pin-to-pin logic delays with counter frequencies up to 227.3 MHz, programmable interconnect that allows any pin to drive any macro cell or I/O, and JTAG-based boundary-scan testing per IEEE 1149.1. The 80 available I/O pins (out of 100 total package pins) share 4 dedicated input clocks and a global clear network, while 3.3 V core operation keeps power dissipation low for industrial and consumer applications.
Architecturally, the device uses EEPROM-based configuration cells, providing non-volatile storage that retains the logic design without external memory. The MAX 3000A macro cells implement sum-of-products logic with configurable flip-flops and a wide fan-in AND-OR structure, while the interconnect matrix (the so-called "Programmable Interconnect Array" or PIA) routes signals between logic array blocks with predictable timing.
Typical applications include bus-interface bridging, address decoding and chip-select generation, state-machine and sequencer implementation, power-up and reset sequencing, peripheral I/O expansion, and glue-logic replacement of discrete 74-series TTL. Its 5 V-tolerant I/O and fast propagation delay also suit industrial control and motor-drive front ends.
When designing with this device, ensure VCCINT is a regulated 3.3 V and VCCIO is set according to the I/O logic level. Decoupling must include 0.1 uF and 1 uF capacitors placed within 5 mm of each supply pin. JTAG chain order should be planned before PCB layout to avoid re-spinning the board for testability.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. The EPM3128ATC100-10NS is the extended-temperature (N suffix) variant of the EPM3128ATC100-10.
ドロップイン代替品: EPM3128ATC100-10NS — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM3128ATC100-10NS （同一形状・フットプリント） — 相違点: Package, Operating Temperature, In-System Programmability, Propagation Delay (tPD), Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM3128ATC100-10N
✅ ドロップイン✓ 在庫あり
$5.2 / 個
データシートを見る →EPM3128ATC100-10
✅ ドロップイン✓ 在庫あり
$8.1 / 個
データシートを見る →EPM3128ATC100-7N
✅ ドロップイン✓ 在庫あり
$3.52 / 個
データシートを見る →EPM3128AFI256-10N
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EPM3128AFC256-7N
✅ ドロップイン✓ 在庫あり
$19.85 / 個
データシートを見る →EPM3128ATC100-10NS 最大定格＆電気的特性
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| User I/Os | 80 |
| ピン数 | 100 |
| パッケージ | TQFP-100 |
| Pin-to-Pin Logic Delay (tPD) | 10 ns |
| Counter Frequency (fCNT) | up to 227.3 MHz |
| Supply Voltage - Core (VCCINT) | 3.3 V |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V |
| Programmability | In-system (ISP), IEEE Std. 1532 |
| Boundary Scan | IEEE 1149.1 JTAG |
| Configuration Memory | EEPROM (non-volatile) |
| 実装タイプ | Surface Mount |
EPM3128ATC100-10NS ピン構成
| ピン 1 | I/O — User I/O (bank 1) |
| ピン 2 | I/O — User I/O (bank 1) |
| ピン 3 | I/O — User I/O (bank 1) |
| ピン 4 | I/O — User I/O (bank 1) |
| ピン 5 | I/O — User I/O (bank 1) |
| ピン 6 | I/O — User I/O (bank 1) |
| ピン 7 | GCLK1 — Global clock input 1 |
| ピン 8 | I/O — User I/O (bank 1) |
| ピン 9 | I/O — User I/O (bank 1) |
| ピン 10 | I/O — User I/O (bank 1) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O (bank 1) |
| ピン 13 | I/O — User I/O (bank 1) |
| ピン 14 | TDI — JTAG test data input |
| ピン 15 | TMS — JTAG test mode select |
| ピン 16 | TCK — JTAG test clock |
| ピン 17 | I/O — User I/O (bank 1) |
| ピン 18 | I/O — User I/O (bank 1) |
| ピン 19 | I/O — User I/O (bank 1) |
| ピン 20 | I/O — User I/O (bank 1) |
| ピン 21 | VCCIO1 — I/O supply bank 1 (3.3 V or 2.5 V) |
| ピン 22 | I/O — User I/O (bank 1) |
| ピン 23 | I/O — User I/O (bank 1) |
| ピン 24 | I/O — User I/O (bank 1) |
| ピン 25 | GCLK2 — Global clock input 2 |
| ピン 26 | I/O — User I/O (bank 1) |
| ピン 27 | I/O — User I/O (bank 1) |
| ピン 28 | I/O — User I/O (bank 1) |
| ピン 29 | I/O — User I/O (bank 1) |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O (bank 1) |
| ピン 32 | I/O — User I/O (bank 1) |
| ピン 33 | I/O — User I/O (bank 1) |
| ピン 34 | I/O — User I/O (bank 1) |
| ピン 35 | I/O — User I/O (bank 1) |
| ピン 36 | I/O — User I/O (bank 1) |
| ピン 37 | I/O — User I/O (bank 1) |
| ピン 38 | I/O — User I/O (bank 1) |
| ピン 39 | VCCINT — Core supply (3.3 V) |
| ピン 40 | I/O — User I/O (bank 1) |
| ピン 41 | I/O — User I/O (bank 1) |
| ピン 42 | I/O — User I/O (bank 1) |
| ピン 43 | I/O — User I/O (bank 1) |
| ピン 44 | I/O — User I/O (bank 1) |
| ピン 45 | GCLK3 — Global clock input 3 |
| ピン 46 | I/O — User I/O (bank 1) |
| ピン 47 | I/O — User I/O (bank 1) |
| ピン 48 | I/O — User I/O (bank 1) |
| ピン 49 | GND — Ground |
| ピン 50 | I/O — User I/O (bank 1) |
| ピン 51 | GCLRn — Global clear (active low) |
| ピン 52 | I/O — User I/O (bank 1) |
| ピン 53 | I/O — User I/O (bank 2) |
| ピン 54 | I/O — User I/O (bank 2) |
| ピン 55 | I/O — User I/O (bank 2) |
| ピン 56 | I/O — User I/O (bank 2) |
| ピン 57 | I/O — User I/O (bank 2) |
| ピン 58 | VCCIO2 — I/O supply bank 2 (3.3 V or 2.5 V) |
| ピン 59 | I/O — User I/O (bank 2) |
| ピン 60 | I/O — User I/O (bank 2) |
| ピン 61 | I/O — User I/O (bank 2) |
| ピン 62 | I/O — User I/O (bank 2) |
| ピン 63 | I/O — User I/O (bank 2) |
| ピン 64 | I/O — User I/O (bank 2) |
| ピン 65 | I/O — User I/O (bank 2) |
| ピン 66 | GND — Ground |
| ピン 67 | I/O — User I/O (bank 2) |
| ピン 68 | I/O — User I/O (bank 2) |
| ピン 69 | I/O — User I/O (bank 2) |
| ピン 70 | I/O — User I/O (bank 2) |
| ピン 71 | I/O — User I/O (bank 2) |
| ピン 72 | I/O — User I/O (bank 2) |
| ピン 73 | I/O — User I/O (bank 2) |
| ピン 74 | I/O — User I/O (bank 2) |
| ピン 75 | TDO — JTAG test data output |
| ピン 76 | GCLK0 — Global clock input 0 |
| ピン 77 | I/O — User I/O (bank 2) |
| ピン 78 | I/O — User I/O (bank 2) |
| ピン 79 | I/O — User I/O (bank 2) |
| ピン 80 | I/O — User I/O (bank 2) |
| ピン 81 | I/O — User I/O (bank 2) |
| ピン 82 | I/O — User I/O (bank 2) |
| ピン 83 | VCCINT — Core supply (3.3 V) |
| ピン 84 | I/O — User I/O (bank 2) |
| ピン 85 | I/O — User I/O (bank 2) |
| ピン 86 | I/O — User I/O (bank 2) |
| ピン 87 | I/O — User I/O (bank 2) |
| ピン 88 | I/O — User I/O (bank 2) |
| ピン 89 | I/O — User I/O (bank 2) |
| ピン 90 | I/O — User I/O (bank 2) |
| ピン 91 | I/O — User I/O (bank 2) |
| ピン 92 | I/O — User I/O (bank 2) |
| ピン 93 | I/O — User I/O (bank 2) |
| ピン 94 | I/O — User I/O (bank 2) |
| ピン 95 | I/O — User I/O (bank 2) |
| ピン 96 | I/O — User I/O (bank 2) |
| ピン 97 | I/O — User I/O (bank 2) |
| ピン 98 | I/O — User I/O (bank 2) |
| ピン 99 | I/O — User I/O (bank 2) |
| ピン 100 | I/O — User I/O (bank 2) |
主な用途
EPM3128ATC100-10NS の用途: 6 件s: Bus Interface Bridging, Address Decoding and Chip-Select Generation, Power-Up and Reset Sequencing, State Machine and Sequencer Implementation, Industrial Control and Motor Drive Front End, Peripheral I/O Expansion and Glue Logic Replacement.
Bus Interface Bridging
The EPM3128ATC100-10NS is well suited to bridge mismatched bus standards such as 8-bit or 16-bit parallel buses between microcontrollers and peripherals. Its 10 ns pin-to-pin delay and 227.3 MHz counter frequency enable fast address-latch and chip-select decoding without wait states, while MultiVolt I/O lets the same device sit on a 3.3 V microcontroller bus and a 5 V peripheral bus simultaneously. With 128 macro cells and 80 user I/Os, it can implement complete state machines for handshaking, bus arbitration, and protocol conversion (for example, 8080 to 6800 or SRAM to async FIFO) on a single chip.
おすすめ
Address Decoding and Chip-Select Generation
The wide AND-OR fan-in of MAX 3000A macro cells makes the EPM3128ATC100-10NS ideal for address-decoding glue logic. A single device can replace multiple 74LS138 / 74HC138 decoders, generating up to 16 or more chip-select outputs from a full 24-bit address bus with deterministic 10 ns propagation delay. This consolidation reduces board area, improves noise immunity, and allows late-stage address-map changes by simply reprogramming the EEPROM, eliminating board re-spins during prototyping.
おすすめ
Power-Up and Reset Sequencing
With its non-volatile EEPROM configuration and instant-on behavior, the EPM3128ATC100-10NS becomes a deterministic reset sequencer for multi-rail systems. Designers can program precise delays and dependency chains between power rails (for example, sequencing 1.8 V, 3.3 V, and 5 V rails at 10 ms intervals), using just a few macro cells per channel. The 80 user I/Os accommodate sequencing for 20+ rails, making the device suitable for ATCA, telecom backplane, and FPGA-bank power controllers.
おすすめ
State Machine and Sequencer Implementation
The EPM3128ATC100-10NS is purpose-built for synchronous state machines. Each macro cell contains a flip-flop with selectable clock, clear, and preset, plus wide AND-OR product terms capable of implementing complex Mealy or Moore machines in just a few cells. With 227.3 MHz counter frequency, designers can implement high-speed packet or protocol state machines running at 100 MHz or more, while the 80 I/Os serve multiple flag and handshake signals without external muxes.
おすすめ
Industrial Control and Motor Drive Front End
The 5 V-tolerant MultiVolt I/O of the EPM3128ATC100-10NS lets it accept inputs directly from 5 V Hall sensors, encoders, and opto-isolated feedback signals in industrial drives. Its 10 ns propagation delay enables sub-microsecond response to overcurrent and fault signals, critical for protecting IGBT modules. Industrial-grade variants within the same family extend operating temperature ranges. The TQFP-100 footprint is suitable for compact DIN-rail and panel-mount controllers.
おすすめ
Peripheral I/O Expansion and Glue Logic Replacement
Designers traditionally implement I/O expansion with 74-series TTL, requiring many small packages. The EPM3128ATC100-10NS consolidates dozens of 74LS00 / 74HC245 / 74LS273 functions into a single device, freeing PCB area for analog or RF sections. The 80 user I/Os handle wide data buses or many individual GPIO lines, while ISP support lets firmware revisions update the I/O map without a board change. Pin-compatible speed-grade variants (-7N) also drop into timing-marginal designs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM3128ATC100-10NS — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM3128ATC100-10N | EPM3128ATC100-10 | EPM3128ATC100-7N | EPM3128AFI256-10N | EPM3128AFC256-7N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 / FBGA-256 | TQFP-100 / FBGA-256 |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 7.5 ns (faster) | 10 ns | 7.5 ns (faster) |
| Counter Frequency | 227.3 MHz | 227.3 MHz | 227.3 MHz | 304 MHz (faster) | 227.3 MHz | 304 MHz (faster) |
| User I/Os | 80 | 80 | 80 | 80 | 100 (FBGA-256 option) | 100 (FBGA-256 option) |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lifecycle | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Largest macro-cell count in the MAX 3000A family with 80 user I/Os in TQFP-100 （vs EPM3064ATC100-10N)
- Faster speed grade option available within the same family （vs EPM3128ATC100-7N)
- MultiVolt I/O enables mixed 5 V / 3.3 V / 2.5 V system integration （vs EPM240T100C5N (MAX II))
設計ノート
Estimated: at maximum toggle frequency of 227 MHz with 80 I/Os at 50% toggle rate, the EPM3128ATC100-10NS draws roughly 250-350 mA from VCCINT (3.3 V). Place one 0.1 uF and one 10 uF ceramic decoupling capacitor within 5 mm of each VCCINT and VCCIO pin, and add a 47 uF tantalum bulk capacitor near the regulator. Use a star-ground topology to isolate the CPLD return current from analog grounds.
The TQFP-100 has 0.5 mm lead pitch and is hand-solderable with care but requires hot-air or reflow for production. Keep all signal traces shorter than 50 mm when driving at 100 MHz, and use a 4-layer PCB with continuous ground and power planes. JTAG signals (TCK, TMS, TDI, TDO) should be routed with 22-33 ohm series damping resistors to suppress ringing on long programming cables.
Do not exceed VCCINT above 3.6 V or VCCIO above 4.0 V, or the EEPROM cells can be damaged. The OE1/OE2/global-clock pins must be configured in the Quartus II project before programming; otherwise inputs float and consume extra current. Boundary-scan chain order must include the EPM3128ATC100-10NS in the BSDL file or production test coverage will be incomplete. Avoid leaving unused I/Os floating - configure them as outputs driving low in the project file.
コンプライアンス情報
RoHS, REACH, and lead-free status not present in the Verified Web Data provided. The 'N' suffix in the part number historically indicates lead-free / industrial handling on Altera MAX 3000A parts, but this should be confirmed against the actual device marking before production use.