EPM3256AFC256-10N vs EPM3512AFC256-23 比較
詳細な並列比較: EPM3256AFC256-10N メーカー: Altera および EPM3512AFC256-23 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 Obsolete仕様比較
| パラメータ | EPM3256AFC256-10N | EPM3512AFC256-23 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $25.95 | $15.75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 5,000 gates | 10,000 |
| Macrocells | 256 | 512 |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| パッケージ | 256-pin FineLine BGA | 256-ball FineLine BGA (FC256), 17 mm x 17 mm |
| Logic Family | CMOS | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| 動作温度 | 0 C to 70 C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Logic Array Blocks (LABs) | — | 16 (32 macrocells each) |
| Maximum Operating Frequency | — | 178.6 MHz |
| Propagation Delay (tPD) | — | 5.5 ns |
| Pin-to-Pin Delay | — | 23 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for FC256] |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) / ISP |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| 実装タイプ | — | Surface Mount (BGA) |