EPM3512AFC256-5C vs EPM3512AFI256-10 比較
詳細な並列比較: EPM3512AFC256-5C メーカー: Altera および EPM3512AFI256-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C Obsolete仕様比較
| パラメータ | EPM3512AFC256-5C | EPM3512AFI256-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $28.95 | $18.75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Maximum Operating Frequency | 95.2 MHz | — |
| Pin-to-Pin Delay (tPD) | 5 ns | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) | — |
| User I/O Pins | 212 (max) | — |
| パッケージ | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch | FBGA-256 (FineLine BGA, 256 balls) |
| 動作温度 | 0 °C to +70 °C (commercial, "C" grade) | 0C to +70C (commercial) |
| Programming Interface | IEEE Std. 1532 / JTAG (4-wire) in-system programmable | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Technology | EEPROM-based macrocell, non-volatile | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Equivalent Gates | — | 10,000 |
| User I/Os | — | 208 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.5 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Propagation Delay | — | 7.5 ns (max, per chipdig summary) |
| Core Voltage | — | 3.3 V |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes, IEEE Std. 1532 (3.3 V ISP) |
| Logic Family | — | CMOS |
| 電源電圧 | — | 3.3 V (core); MultiVolt I/O to 5.0 V |