EPM3512AFI256-10 vs EPM3512AFI256-7 比較
詳細な並列比較: EPM3512AFI256-10 メーカー: Intel および EPM3512AFI256-7 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AFI256-10 | EPM3512AFI256-7 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.75 | $15.95 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Equivalent Gates | 10,000 | — |
| Macrocells | 512 | 512 |
| User I/Os | 208 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.5 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Propagation Delay | 7.5 ns (max, per chipdig summary) | — |
| Core Voltage | 3.3 V | — |
| MultiVolt I/O Levels | 5.0 V / 3.3 V / 2.5 V | — |
| Process Technology | CMOS EEPROM | 0.30 µm CMOS EEPROM |
| In-System Programmability | Yes, IEEE Std. 1532 (3.3 V ISP) | IEEE Std. 1532 compliant via JTAG |
| パッケージ | FBGA-256 (FineLine BGA, 256 balls) | 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch |
| 動作温度 | 0C to +70C (commercial) | — |
| Logic Family | CMOS | — |
| RoHS ステータス | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: confirm from data] |
| 電源電圧 | 3.3 V (core); MultiVolt I/O to 5.0 V | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10,000 |
| Logic Array Blocks (LABs) | — | 32 (16 macrocells each) |
| User I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX value] |
| Supply Voltage VCCINT | — | 3.3 V |
| MultiVolt I/O Voltage | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| Operating Temperature (Industrial) | — | -40 °C to +85 °C |
| 実装タイプ | — | Surface Mount (BGA) |