EPM3512AFI256-10N vs EPM3512ATI256-10N 比較
詳細な並列比較: EPM3512AFI256-10N メーカー: Altera および EPM3512ATI256-10N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ ラストタイムバイ仕様比較
| パラメータ | EPM3512AFI256-10N | EPM3512ATI256-10N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.75 | $19.85 |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | 10,000 |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | — |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| パッケージ | 256-ball FineLine BGA (FBGA-256) | 256-pin BGA (TI256) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | -40 °C to +85 °C (industrial) | — |
| RoHS ステータス | Compliant | [DATA_NEEDED: RoHS status] |
| Speed Grade | -10 (10 ns tPD) | -10 (10 ns pin-to-pin delay) |
| Manufacturer | — | Intel (formerly Altera Corporation) |
| Device | — | EPM3512A |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 212 |
| 動作温度 | — | -40C to +85C (Industrial) |
| Core Voltage | — | 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std 1149.1 boundary-scan, 4-pin JTAG |
| Programmable Security Bit | — | Yes (design protection) |
| ライフサイクル状態 | — | Obsolete / Last Time Buy (per Altera product discontinuation notices) |