EPM3512AQC208-10-10N vs EPM3512AQI208-10N 比較
詳細な並列比較: EPM3512AQC208-10-10N メーカー: Altera および EPM3512AQI208-10N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N Obsolete仕様比較
| パラメータ | EPM3512AQC208-10-10N | EPM3512AQI208-10N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $31.20 | $12.90 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | — |
| Usable Gates | 10,000 | — |
| User I/Os | 172 | 172 (max), 208-pin package |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | 10 ns |
| Maximum Frequency (fCNT) | 87 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan (JTAG) | Yes, IEEE 1149.1 | — |
| PCI-SIG Compliance | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) | — |
| 動作温度 | 0 °C to +70 °C (commercial) | 0C to 70C |
| パッケージ | 208-pin PQFP (Plastic Quad Flat Pack) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Family | — | CMOS EEPROM-based |
| Macro Cells | — | 512 |
| Logic Array Blocks (LABs) | — | 12 |
| 電源電圧 | — | 3.3 V |
| I/O Standards | — | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) |
| Package Type | — | PQFP-208 (FINE LINE BGA-style 256-pin land) |
| Pins | — | 256 (package), 208 used |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Compliance | — | RoHS status unknown from data |
| Boundary Scan | — | Built-in BST (IEEE 1149.1) |
| Configuration Memory | — | On-chip EEPROM, non-volatile |