EPM3512AQC208-10-10N vs EPM3512AQI208-10N 对比

详细并排对比 EPM3512AQC208-10-10N 出自 Altera 和 EPM3512AQI208-10N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AQC208-10-10N EPM3512AQI208-10N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $31.20 $12.90
Family MAX 3000A MAX 3000A
Macrocells 512 —
Usable Gates 10,000 —
User I/Os 172 172 (max), 208-pin package
Logic Elements / LABs 16 Logic Array Blocks —
Propagation Delay (tPD) 10 ns (-10 speed grade) 10 ns
Maximum Frequency (fCNT) 87 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V —
Process Technology CMOS EEPROM —
In-System Programmability Yes, IEEE Std. 1532 compliant —
Boundary-Scan (JTAG) Yes, IEEE 1149.1 —
PCI-SIG Compliance PCI Local Bus Specification Rev 2.2 (at -10 speed grade) —
工作温度 0 °C to +70 °C (commercial) 0C to 70C
封装 208-pin PQFP (Plastic Quad Flat Pack) —
安装类型 Surface Mount Surface Mount
Lead-Free / RoHS [DATA_NEEDED: RoHS status] —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Family — CMOS EEPROM-based
Macro Cells — 512
Logic Array Blocks (LABs) — 12
电源电压 — 3.3 V
I/O Standards — MultiVolt (2.5 V / 3.3 V / 5 V tolerant)
Package Type — PQFP-208 (FINE LINE BGA-style 256-pin land)
Pins — 256 (package), 208 used
Programming Interface — JTAG (IEEE 1149.1) / ISP (IEEE 1532)
Compliance — RoHS status unknown from data
Boundary Scan — Built-in BST (IEEE 1149.1)
Configuration Memory — On-chip EEPROM, non-volatile

数据手册与资源

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