EPM3512AQC208-10S vs EPM3512AQC208-7N 比較
詳細な並列比較: EPM3512AQC208-10S メーカー: Altera および EPM3512AQC208-7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC208-10S | EPM3512AQC208-7N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $41.41 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | — |
| Usable Gates | 1750 | — |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 32 |
| パッケージ | 208-pin FineLine BGA-256 | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| User I/Os | 208 | 172 |
| Speed Grade | -10 (tPD1 = 7.5 ns) | -7 |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | — |
| Supply Voltage - VCCINT (internal) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM | — |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | — |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | — |
| 動作温度 | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Logic Family | CMOS | — |
| Process Technology | EEPROM-based CMOS | 0.30 µm CMOS EEPROM |
| RoHS ステータス | [DATA_NEEDED: rohs_status] | Compliant |
| Logic Capacity | — | 512 macrocells, 10,000 usable gates |
| Macrocells per LAB | — | 16 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | — | 4 (MultiVolt) |
| Supported I/O Standards | — | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Configuration | — | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1149.1 BST + IEEE 1532 ISP |