EPM3512AQC208-10S vs EPM3512AQC208-7N Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-10S par Altera et EPM3512AQC208-7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3512AQC208-10S | EPM3512AQC208-7N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $41,41 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | — |
| Usable Gates | 1750 | — |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 32 |
| Boîtier | 208-pin FineLine BGA-256 | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| User I/Os | 208 | 172 |
| Speed Grade | -10 (tPD1 = 7.5 ns) | -7 |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | — |
| Supply Voltage - VCCINT (internal) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM | — |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | — |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | — |
| Température de fonctionnement | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Logic Family | CMOS | — |
| Process Technology | EEPROM-based CMOS | 0.30 µm CMOS EEPROM |
| Statut RoHS | [DATA_NEEDED: rohs_status] | Compliant |
| Logic Capacity | — | 512 macrocells, 10,000 usable gates |
| Macrocells per LAB | — | 16 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | — | 4 (MultiVolt) |
| Supported I/O Standards | — | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Configuration | — | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1149.1 BST + IEEE 1532 ISP |