EPM3512AQC20810 vs EPM3512AQC208-10N 比較
詳細な並列比較: EPM3512AQC20810 メーカー: Altera および EPM3512AQC208-10N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC20810 | EPM3512AQC208-10N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.80 | $42.80 |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CPLD (EEPROM-based, non-volatile) | — |
| Macro Cells | 512 | — |
| User I/Os | 172 | 172 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates (equivalent) | 10000 | — |
| パッケージ | 208-pin PQFP (PQ208) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Speed Grade | -10 (tPD = 10 ns) | -10 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 132 MHz | 227.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 compliant | — |
| Operating Temperature (commercial) | 0 °C to +70 °C | — |
| Process Technology | 0.30 µm CMOS EEPROM | CMOS EEPROM |
| Configuration Memory | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in verified web data] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Usable Gates | — | Up to 10,000 |
| 電源電圧 | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |
| 動作温度 | — | 0 C to 70 C (commercial) |