EPM3512AQC210-7 vs EPM3512AQC208-10N 比較
詳細な並列比較: EPM3512AQC210-7 メーカー: Altera および EPM3512AQC208-10N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC210-7 | EPM3512AQC208-10N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.85 | $42.80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 172 | — |
| Dedicated Input Pins | 12 | — |
| パッケージ | PQFP-208 | 208-pin PQFP (Plastic Quad Flat Pack) |
| ピン数 | 208 | — |
| 実装タイプ | Surface Mount | — |
| Operating Voltage (Core) | 3.3 V | — |
| Min Supply Voltage | 3.0 V | — |
| Max Supply Voltage | 3.6 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Pin-to-Pin Delay | 7 ns (speed grade -7) | 4.5 ns (-10 speed grade) |
| Speed Grade | 7 ns | -10 |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 C to 70 C (commercial) |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status not in verified web data] |
| Usable Gates | — | Up to 10,000 |
| User I/Os | — | 172 |
| 電源電圧 | — | 3.3 V |
| Maximum Internal Frequency | — | 227.3 MHz |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |