EPM3512AQC210-7 vs EPM3512AQC208-7N 比較
詳細な並列比較: EPM3512AQC210-7 メーカー: Altera および EPM3512AQC208-7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC210-7 | EPM3512AQC208-7N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.85 | $41.41 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 32 |
| Maximum User I/O Pins | 172 | — |
| Dedicated Input Pins | 12 | — |
| パッケージ | PQFP-208 | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| ピン数 | 208 | — |
| 実装タイプ | Surface Mount | — |
| Operating Voltage (Core) | 3.3 V | — |
| Min Supply Voltage | 3.0 V | — |
| Max Supply Voltage | 3.6 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Pin-to-Pin Delay | 7 ns (speed grade -7) | — |
| Speed Grade | 7 ns | -7 |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial) |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | Compliant |
| Logic Capacity | — | 512 macrocells, 10,000 usable gates |
| Macrocells per LAB | — | 16 |
| User I/Os | — | 172 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | — | 4 (MultiVolt) |
| Supported I/O Standards | — | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Configuration | — | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1149.1 BST + IEEE 1532 ISP |