EPM3512AQI208-10N vs EPM3512AQC208-10N 比較
詳細な並列比較: EPM3512AQI208-10N メーカー: Intel および EPM3512AQC208-10N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQI208-10N | EPM3512AQC208-10N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $12.90 | $42.80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS EEPROM-based | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 12 | 16 |
| User I/Os | 172 (max), 208-pin package | 172 |
| Propagation Delay (tPD) | 10 ns | — |
| 電源電圧 | 3.3 V | 3.3 V |
| I/O Standards | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) | MultiVolt (1.8V / 2.5V / 3.3V) |
| Package Type | PQFP-208 (FINE LINE BGA-style 256-pin land) | — |
| Pins | 256 (package), 208 used | — |
| 動作温度 | 0C to 70C | 0 C to 70 C (commercial) |
| 実装タイプ | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | — |
| Compliance | RoHS status unknown from data | — |
| Boundary Scan | Built-in BST (IEEE 1149.1) | — |
| Configuration Memory | On-chip EEPROM, non-volatile | — |
| Macrocells | — | 512 |
| Usable Gates | — | Up to 10,000 |
| パッケージ | — | 208-pin PQFP (Plastic Quad Flat Pack) |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| Speed Grade | — | -10 |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status not in verified web data] |