EPM5016DC-20 vs EPM5016PC-1 比較
詳細な並列比較: EPM5016DC-20 メーカー: Altera および EPM5016PC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5016DC-20 | EPM5016PC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.50 | $9.95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | 35 ns |
| 最大クロック周波数 | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | — |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | Non-compliant (PDIP with SnPb leads, pre-RoHS era) |
| Usable Gates | — | 200 |
| Logic Array Blocks (LABs) | — | 1 |
| Maximum Frequency (fMAX) | — | 62 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time ns] |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Supply Current (ICC) | — | 50 mA typical |
| パッケージ | — | PDIP-20 (plastic DIP, through-hole) |
| ピン数 | — | 20 |
| Configuration Memory | — | CMOS EEPROM (UV-erasable) |
| Programming Interface | — | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) |