EPM5016DC-20 vs EPM5016PC-1 Comparaison
Comparaison détaillée côte à côte de EPM5016DC-20 par Altera et EPM5016PC-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5016DC-20 | EPM5016PC-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,50 | $9,95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | 35 ns |
| Fréquence d'horloge maximale | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | — |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (PDIP with SnPb leads, pre-RoHS era) |
| Usable Gates | — | 200 |
| Logic Array Blocks (LABs) | — | 1 |
| Maximum Frequency (fMAX) | — | 62 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time ns] |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Supply Current (ICC) | — | 50 mA typical |
| Boîtier | — | PDIP-20 (plastic DIP, through-hole) |
| Nombre de broches | — | 20 |
| Configuration Memory | — | CMOS EEPROM (UV-erasable) |
| Programming Interface | — | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) |